1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a transistor having silicide films formed both on source/drain regions and a gate electrode in self-aligned fashion, namely a transistor having a self-aligned silicide (salicide) structure.
2. Description of the Related Art
With demands in reduction in size and high integration of a semiconductor device, a gate electrode has been more and more reduced in both size and thickness, and source and drain regions have been made to have a shallower junction depth. This causes a gate wiring to have a greater resistance, and also causes source and drain regions to have a greater sheet resistance. In addition, higher integration of a semiconductor device causes a longer wire length, and, on the other hand, a semiconductor device is demanded to operate at higher speed. As a result, it is no longer possible for a conventional polysilicon gate electrode to provide a semiconductor device having desired performances.
In order to solve such a problem, there has been suggested and used a salicide (self-aligned silicide) structure in which there are formed metal silicide films such as titanium silicide are formed both on a polysilicon gate electrode and source/drain regions of a transistor in self-aligned fashion to thereby reduce resistance of a gate electrode and source/drain regions.
However, the above mentioned salicide structure poses a problem that a silicon dioxide film reacts with titanium on a sidewall to thereby produce titanium, though in a quite small amount, to thereby cause short-circuits between a gate electrode and source/drain regions.
As a countermeasure to the problem, Japanese Unexamined Patent Publication No. 4-34933 has suggested carrying out wet etching for removal of a portion at which the short-circuits is to take place. Hereinbelow will be explained the method suggested in the above mentioned Publication, with reference to FIGS. 1A to 1D which are cross-sectional views showing respective step of the method.
As illustrated in Fig. 1A, a gate polysilicon film 3 is formed on a silicon substrate 1 with a gate insulating film 2 sandwiched therebetween, and then a sidewall 5 is formed around a side surface of the gate polysilicon film 3. The sidewall 5 is made of insulating material. The silicon substrate 1 has source and drain regions 4 therein a part of which is in exposure to atmosphere. A resultant is entirely covered with a titanium film 6 by sputtering or evaporation.
Then, the semiconductor substrate 1 is thermally treated to thereby form titanium silicide films 7 on both the gate polysilicon film 3 and the source and drain regions 4, as illustrated in FIG. 1B.
Then, non-reacted portions 6a of the titanium film 6 are etched for removal by using an etchant such as a mixture solution of H.sub.2 SO.sub.4 and H.sub.2 O.sub.2 which removes titanium in titanium silicide with great etching selectivity. Regardless of this etching, portions 7a of the titanium silicide film 7, though in a quite small amount, remain non-etched on the sidewall 5, as illustrated in Fig. 1C.
Thereafter, the portions 7a of the titanium silicide film 7 are removed by using an etchant such as a mixture solution of NH.sub.4 OH and H.sub.2 O.sub.2 which removes titanium in titanium silicide with small etching selectivity. Thus, the titanium silicide having been formed on the sidewall is removed, and hence it is possible to prevent occurrence of short-circuits between the gate electrode 3 and the source and drain regions 4.
However, the above mentioned method suggested in Japanese Unexamined Patent Publication No. 4-34933 has two problems as follows: one of them is that titanium silicide films formed on both the gate polysilicon film and the source and drain regions are also etched out simultaneously with the removal of the titanium silicide film remaining non-etched on the sidewall, resulting in an increase in a resistance in the gate electrode and the source and drain regions; the other is that a resistance would be further increased in the gate electrode and the source and drain regions, since interfaces between the titanium silicide film and the gate polysilicon film and also between the titanium silicide film and the silicon substrate are side-etched.
For another example, Japanese Unexamined Patent Publication No. 7-99171 has suggested a method of fabricating a MOS transistor which method is capable of decreasing a sheet resistance without occurrence of bridging. This method includes the steps of forming a gate electrode on a silicon substrate, forming source and drain diffusion layers, depositing a titanium film all over a resultant and thermally treat the resultant to thereby form TiSi.sub.2 layers, and selectively removing non-reacted titanium and titanium compounds other than TiSi.sub.2 by using a mixture solution of H.sub.2 O.sub.2 and H.sub.2 SO.sub.4 (H.sub.2 O.sub.2 :H.sub.2 SO.sub.4 =1:1).
However, this method has the same problems as those of the first mentioned prior method, namely the above mentioned two problems.